Design and performance evaluation of dynamic interconnection networks for VLSI implementation
There are a number of problems in designing very-large-scale-integrated circuits interconnection network such as chip layout of switch nodes, logic partition of networks, clock synchronization, and delay analysis as well as chip area. The chip area and time delay problems constitute the core of this dissertation. The area of a layout is defined as the area of the smallest rectangle containing all the nodes and links. A node represents a transistor or a small cluster of transistors: as such, it receives and transmits signals over its connecting wires. A number of interconnection networks which can be used to connect multiple processors to multiple memory are presented and the most powerful and reliable among these that minimize the links and the time delay are selected. A general simulation model to be used for the development of the area and time delay models in VLSI chip is proposed. The general model is designed to eliminate the basic disadvantages of the previous model. Furthermore, it can be adapted to any size of circuit switching networks and to any size of switches. This general simulation model is also used for analyzing and comparing the performance characteristics of various types of interconnection networks in a VLSI environment. A series of experiments have been conducted to gather data performance from a VLSI area and time delay model, using the proposed general simulation model. It is shown that with this simulation model significant results are obtained over the previous models. Further, using our general model, we found that the performance of the multistage network has better area, time delay, and can be cost effective if implemented for VLSI implementation. Furthermore, for (4 * 4) switches, the multistage networks have much better performance over the (2 * 2) switches.
- Research Organization:
- Dayton Univ., OH (USA)
- OSTI ID:
- 6596418
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
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SEMICONDUCTOR DEVICES
DESIGN
PERFORMANCE TESTING
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTER NETWORKS
COMPUTERIZED SIMULATION
EQUIPMENT INTERFACES
INFORMATION SYSTEMS
MULTILEVEL ANALYSIS
SWITCHING CIRCUITS
TIME DELAY
TRANSISTORS
ELECTRONIC CIRCUITS
SIMULATION
TESTING
990200* - Mathematics & Computers
990300 - Information Handling