A Josephson four-bit full adder using direct coupled functional gates

Conference · Fri Mar 01 00:00:00 EST 1985 · IEEE Trans. Magn.; (United States)

OSTI ID:6485209

Matheron, G; Migny, Ph; Sie, O

A Josephson 4-bit full adder circuit using functional direct coupled gates has been designed and studied through computer simulations. The circuit consists of only 27 gates taken from a complete logic family composed of OR, AND, EXOR and MAJORITY gates. The proposed adder scheme needs 180 Josephson junctions and 150 thin film resistors. The computed critical path delay was found 180 ps/4bits for carry propagation, with a power dissipation estimated to be less than 100 ..mu..W on the basis of a Nb/Pb-In technology with 4 ..mu..m minimum linewidth and with a Josephson current density of 1 000 A/cm/sup 2/. The worst case total add time for the 4 bits has been found less than 300 ps.

• Research Organization: Commissariat a l'Energie Atomique, LETI-IRDI, Grenoble
• OSTI ID: 6485209
• Report Number(s): CONF-840937-
• Journal Information: IEEE Trans. Magn.; (United States), Vol. MAG-21:2; Conference: Applied superconductivity conference, San Diego, CA, USA, 9 Sep 1984
• Country of Publication: United States
• Language: English

Related Subjects

71 CLASSICAL AND QUANTUM MECHANICS
GENERAL PHYSICS
LOGIC CIRCUITS
PERFORMANCE
COMPUTERIZED SIMULATION
CURRENT DENSITY
GATING CIRCUITS
JOSEPHSON JUNCTIONS
RESISTORS
ELECTRICAL EQUIPMENT
ELECTRONIC CIRCUITS
EQUIPMENT
JUNCTIONS
SIMULATION
SUPERCONDUCTING JUNCTIONS
420201* - Engineering- Cryogenic Equipment & Devices