Hector; A hierarchically structured shared-memory multiprocessor
- Univ. of Toronto (CA)
This paper reports on the architecture of the Hector multiprocessor exploits current microprocessor technology to produce a machine with a good cost/performance trade-off. A key design feature of Hector is its interconnection backplane, which can accommodate future technology because it uses simple hardware with short critical paths in logic circuits and short lines in the interconnection network. The system is reliable and flexible, and can be realized at a relatively low cost. An important aim of the Hector project is to develop an architecture suitable for a general-purpose multiprocessor whose cost is directly proportional to size. Thus, an entry-level machine would be inexpensive, but can scale to larger sizes. The accommodate configurations with varying numbers of processors, Hector has a hierarchical structure. Bit-parallel rings interconnect small bus sections. The buses and rings can transfer data independently of each other, so aggregate bandwidth increases proportionally with the number of these units. Hector is suitable for single jobs with many parallel tasks, as well as for concurrent execution of multiple jobs consisting of predominantly serial tasks. In other words, it is effective in a Unix environment, as well as in such highly parallel commercial and scientific applications as transaction systems, finite-element analysis, and computer-aided design.
- OSTI ID:
- 6253818
- Journal Information:
- Computer; (United States), Vol. 24:1; ISSN 0018-9162
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
PARALLEL PROCESSING
COMPUTER ARCHITECTURE
COMPUTER-AIDED DESIGN
FINITE ELEMENT METHOD
LOGIC CIRCUITS
MEMORY MANAGEMENT
TASK SCHEDULING
DATA PROCESSING
DESIGN
ELECTRONIC CIRCUITS
NUMERICAL SOLUTION
PROCESSING
PROGRAMMING
990200* - Mathematics & Computers