Implementation of the PIPE processor
- Univ. of California at Davis, CA (US)
- Univ. of Colorado at Boulder, CO (US)
In the early 1980s, the PIPE (Parallel Instruction with Pipelined Execution) research project was initiated to investigate high-performance computer architectures for VLSI implementation. One of the primary project goals was to devise architectural methods to minimize the impact of off-chip memory accesses on processor performance. Crossing the boundary between the processor chip and external memory is one of the main impediments to achieving high performance in VLSI processors, and the problem is becoming more severe. Because the on-chip clock frequency of a VLSI processor chip is increasing at a much higher rate than external memory speeds, it will soon take 10 to 100 processor clock cycles to perform a single external memory reference. Because of the unique features in PIPE and the important problems it addresses, the PIPE architecture implementation should interest not only those exploring decoupled access/execute architectures, but also conventional processor designers. In the paper the authors present an outline of the machine, a description of the processor, and an evaluation of the valuable lessons learned via the implementation.
- OSTI ID:
- 5987557
- Journal Information:
- Computer; (United States), Vol. 24:1; ISSN 0018-9162
- Country of Publication:
- United States
- Language:
- English
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