ASIC (Application Specific Integrated Circuit) replacement for an SSI (Small Scale Integrated) component design a case study
This case study covers the practical issues of design-for- functionality, design-for-simulation, and design-for-testability in replacing aging SSI component designs with ASIC gate arrays. The replacement of a 169-TTL-component design with a CMOS ASIC gate array is presented. Maintaining existing functionality is accomplished through a series of ordered conversion steps that minimize the probability of error in the conversion. Design modifications, such as the addition of initialization circuitry, were necessary to take advantage of CAE simulation tools. The faster ASIC technology coupled with design modifications allowed the time-to-simulate to be decreased by a factor of 10,000. A unique pseudo-random number generation/signature analysis technique is presented that interrogates highly sequential designs. The testability scheme and other design techniques improved stuck-at fault coverage by more than 640%. The economic advantages, knowledge gained, and the tools developed that are applicable to future design work are also discussed. 12 figs.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (USA)
- DOE Contract Number:
- AC04-76DP00789
- OSTI ID:
- 5843985
- Report Number(s):
- SAND-89-0841C; CONF-8909146-1; ON: DE89013494
- Resource Relation:
- Conference: 2. annual IEEE/ASIC seminar and exhibit, Rochester, NY, USA, 25-28 Sep 1989; Other Information: Portions of this document are illegible in microfiche products
- Country of Publication:
- United States
- Language:
- English
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