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Title: Wafer-level radiation testing for hardness assurance

Conference · · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)
DOI:https://doi.org/10.1109/23.124151· OSTI ID:5832611
; ; ; ;  [1];  [2];  [3]
  1. Sandia National Labs., Albuquerque, NM (United States)
  2. L and M Technology, Albuquerque, NM (US)
  3. Mission Research Corp., Albuquerque, NM (United States)

This paper reports that, to implement the Qualified Manufacturers List (QML) approach to hardness assurance in a practical and cost-effective manner, one must identify technology parameters that affect radiation hardness and bring them under statistical process control. To aid this effort, the authors have developed a wafer-level test system to map test-structure and IC response across a wafer. This system permits current-voltage and charge-pumping measurements on transistors, and high-frequency capacitance-voltage measurements on capacitors. For frequencies up to 50 MHz, the system provides a complete menu of functional and parametric IC tests. Wafer maps and histograms of test-structure and IC response are presented for a 1.2-{mu}m radiation-hardened CMOS technology to illustrate the capabilities of the wafer-level test system. Statistical and deterministic approaches to correlate test structure and IC response are discussed for this technology.

DOE Contract Number:
AC04-76DP00789
OSTI ID:
5832611
Report Number(s):
CONF-910751-; CODEN: IETNA
Journal Information:
IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), Vol. 38:6; Conference: Institute of Electrical and Electronic Engineers (IEEE) annual international nuclear and space radiation effects conference, San Diego, CA (United States), 15-19 Jul 1991; ISSN 0018-9499
Country of Publication:
United States
Language:
English