SEU characterization and design dependence of the SA3300 microprocessor

Conference · Sat Dec 01 00:00:00 EST 1990 · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA)

DOI:https://doi.org/10.1109/23.101202· OSTI ID:5767746

Sexton, F W; Treece, R K; Hass, K J; Hash, G L; Axness, C L ^[1]; Hughes, K L ^[2]; Buchner, S P; Kang, K ^[3]

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1. Sandia National Labs., Albuquerque, NM (USA)
2. L and M Associates, Albuquerque, NM (US)
3. Martin Marietta Labs., Baltimore, MD (USA)

The SEU vulnerability of the SA3300 16-bit microprocessor has been characterized, and the effects of two different design revisions on error rate have been explored. The authors have found that the threshold for upset depends on the data pattern written into the general purpose registers. With all bits in the general purpose registers set to logic one, a design with 2-{mu}m n- and p-channel transistor lengths had a threshold LET of 35 MeV-cm{sup 2}/mg at 25{degrees} C and 4.5 volt operation. With all zero's stored in the registers the upset threshold increased by more than a factor of two to 83 MeV- cm{sup 2}/mg. A second design revision, with 1.25-{mu}m and 1.75-{mu}m n- and p-channel transistor lengths, respectively, was more vulnerable to upset, but exhibited a smaller dependence on logic state.

• DOE Contract Number: AC04-76DP00789
• OSTI ID: 5767746
• Report Number(s): CONF-900723-; CODEN: IETNA; TRN: 91-014902
• Journal Information: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (USA), Vol. 37:6; Conference: 27. IEEE annual conference on nuclear and space radiation effects, Reno, NV (USA), 16-20 Jul 1990; ISSN 0018-9499
• Country of Publication: United States
• Language: English

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