Reconfigurable parallel pipelines for fault tolerance
A pipeline architecture is an efficient method of gaining increased performance in digital circuitry, yet it is highly susceptible to failure. A single fault in any segment would cause a total failure of the pipeline. Modular redundancy techniques are inefficient and costly for systems with segments of high complexity. Reconfigurable parallel pipelines can be utilised to implement fault tolerance while also increasing performance. Initially, the performance of the system is increased by the number of parallel pipelines. When a segment fails, the other segments in that pipeline become available as spares to mask subsequent faults in the other pipelines. The mean time to failure of a reconfigurable parallel pipeline system is the same as or greater than a single pipeline with modular redundancy. However, the parallel pipeline system has a greater mean computation to failure due to its graceful degradation property. 15 references.
- OSTI ID:
- 5179247
- Report Number(s):
- CONF-820908-
- Resource Relation:
- Conference: IEEE conference on circuits and computers, New York, NY, USA, 29 Sep 1982
- Country of Publication:
- United States
- Language:
- English
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