Design methodology for VLSI processors
A design methodology for VLSI processors was developed. It is based on five major design levels - microarchitecture, functional block, circuit, interconnect, and process - and the interactions between them. In addition to top-down synthesis, this method formally incorporates the feedback of information from the lower design levels to the higher levels. A preliminary design phase that considers the effects of the lowest levels - circuit, interconnect, and process - on design at the highest level - microarchitecture - is described. After preliminary design, design alternates between synthesis and analysis steps as the designers proceed from the highest level to the lower levels. SOAR (Smalltalk on a RISC), a 32-bit microprocessor designed for the efficient execution of compiled Smalltalk provides a case study of this methodology. The chip, implemented in 4-micron, single-level metal NMOS technologies, has a cycle time of 400 ns. Pipelining allows an instruction to start each cycle with the exception of loads and stores. The processor contains 35,700 transistors, is 320 x 432 mils, dissipates 3 watts, and is assembled in an 84-lead pin-grid array package. The methodology that included a large CAD effort provided functioning chips on first silicon.
- Research Organization:
- California Univ., Berkeley (USA)
- OSTI ID:
- 5099520
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
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