Influence of the charge trap density distribution in a gate insulator on the positive-bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors
We investigated the positive-bias stress (PBS) instability of thin film transistors (TFTs) composed of different types of first-gate insulators, which serve as a protection layer of the active surface. Two different deposition methods, i.e., the thermal atomic layer deposition (THALD) and plasma-enhanced ALD (PEALD) of Al{sub 2}O{sub 3}, were applied for the deposition of the first GI. When THALD was used to deposit the GI, amorphous indium-gallium-zinc oxide (a-IGZO) TFTs showed superior stability characteristics under PBS. For example, the threshold voltage shift (ΔV{sub th}) was 0 V even after a PBS time (t{sub stress}) of 3000 s under a gate voltage (V{sub G}) condition of 5 V (with an electrical field of 1.25 MV/cm). On the other hand, when the first GI was deposited by PEALD, the ΔV{sub th} value of a-IGZO TFTs was 0.82 V after undergoing an identical amount of PBS. In order to interpret the disparate ΔV{sub th} values resulting from PBS quantitatively, the average oxide charge trap density (N{sub T}) in the GI and its spatial distribution were investigated through low-frequency noise characterizations. A higher N{sub T} resulted during in the PEALD type GI than in the THALD case. Specifically, the PEALD process on a-IGZO layer surface led to an increasing trend of N{sub T} near the GI/a-IGZO interface compared to bulk GI owing to oxygen plasma damage on the a-IGZO surface.
- OSTI ID:
- 22591671
- Journal Information:
- Applied Physics Letters, Vol. 108, Issue 18; Other Information: (c) 2016 Author(s); Country of input: International Atomic Energy Agency (IAEA); ISSN 0003-6951
- Country of Publication:
- United States
- Language:
- English
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