Reduced Common-Mode Voltage PWM Scheme for Full-SiC Three-Level Uninterruptible Power Supply With Small DC-Link Capacitors
- Virginia Polytechnic Inst. and State Univ. (Virginia Tech), Blacksburg, VA (United States)
- ABB Corporate Research Center, Raleigh, NC (United States)
In this article, a pulsewidth modulation (PWM) scheme for three-level full-SiC uninterruptible power supplies is developed to achieve a high power density. Two key passive components are selected for size reduction of the ac-ac stage: common-mode (CM) EMI filter, and dc-link capacitors. To reduce the CM noise, a new vector combination is proposed based on synchronous switching among three-phases. The proposed combinations align CM voltage (CMV) to be a single pulse per switching period. Owing to the simple shape, CMV cancellation between a three-level rectifier and inverter can be maximally utilized. A transition between the three combinations can control the drift of neutral point voltage. An equivalent carrier-based implementation is developed. Second, a simple algorithm to compensate neutral point voltage fluctuation is proposed both for differential mode (DM) and CM output voltage. Low-order harmonics on three-phase currents and an additional high-frequency CM noise by misaligned switching instant can be eliminated. The proposed compensation can be implemented by a simple correction on carrier slopes and injected zero-sequence voltage. The proposed PWM scheme is verified with 20-kW full-SiC UPS switching at 60 kHz with 140 μF dc-link capacitors.
- Research Organization:
- North Carolina State University, Raleigh, NC (United States)
- Sponsoring Organization:
- USDOE Office of Energy Efficiency and Renewable Energy (EERE), Energy Efficiency Office. Advanced Manufacturing Office
- Grant/Contract Number:
- EE0006521
- OSTI ID:
- 1799221
- Journal Information:
- IEEE Transactions on Power Electronics, Vol. 35, Issue 8; ISSN 0885-8993
- Publisher:
- IEEECopyright Statement
- Country of Publication:
- United States
- Language:
- English
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