This package provides a complete set of FPGA logic and driver software for the LBNL Interim SNS (Spallation Neutron Source) LLRF (Low Level Radio Frequency) cavity control system, plus a hardware-software cosimulation framework that can demonstrate correct operation of the code. The controls are organized in a traditional three-tier layout. Tier 1 (hardware access): Verilog code targeted at the XC2S15O FPGA that lies at the center of the custom hardware, Includes a direct digital frequency synthesizer (DDS), a low-latency vector PI feedback control loop, four-channel vector waveform capture, and support for on-board housekeeping circuitry. Tier 2 (network presentation): C code targeted at a 32-bit microcontroller, which has a direct connection to both the FPGA and to Ethemet. This layer is itself divided into a HAL (hardware abstraction layer) to mediate access to the FPGA registers, a driver to organize all the application-specific computations (including a waveform curve fit that determines cavity detuning), and a toy network access protocol. Tier 3 (operator interface): A Tcl program that exchanges data with tier 2, and gives the operator a virtual control panel for the hardware In the production SNS installation, the toy network access protocol and tier 3 are replaced with EPICS (http://www.aps.anl.gov/epics/). The code given here is dramatically smaller and simpler than EPICS, yet gives enough functionality to demonstrate proper operation of an RF cavity. The SNS facility now uses three generations of LLRF control hardware. This package is intended to be used in all of them, but is so far only tested on the second ("Interim") generation hardware. It may also be adaptable to future LLRF projects at LBNL, other National Labs, and worldwide.
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@misc{osti_1245751,
title = {LBNL LLRF Controls Suite, Version 00},
author = {Doolittle, Lawrence R.},
abstractNote = {This package provides a complete set of FPGA logic and driver software for the LBNL Interim SNS (Spallation Neutron Source) LLRF (Low Level Radio Frequency) cavity control system, plus a hardware-software cosimulation framework that can demonstrate correct operation of the code. The controls are organized in a traditional three-tier layout. Tier 1 (hardware access): Verilog code targeted at the XC2S15O FPGA that lies at the center of the custom hardware, Includes a direct digital frequency synthesizer (DDS), a low-latency vector PI feedback control loop, four-channel vector waveform capture, and support for on-board housekeeping circuitry. Tier 2 (network presentation): C code targeted at a 32-bit microcontroller, which has a direct connection to both the FPGA and to Ethemet. This layer is itself divided into a HAL (hardware abstraction layer) to mediate access to the FPGA registers, a driver to organize all the application-specific computations (including a waveform curve fit that determines cavity detuning), and a toy network access protocol. Tier 3 (operator interface): A Tcl program that exchanges data with tier 2, and gives the operator a virtual control panel for the hardware In the production SNS installation, the toy network access protocol and tier 3 are replaced with EPICS (http://www.aps.anl.gov/epics/). The code given here is dramatically smaller and simpler than EPICS, yet gives enough functionality to demonstrate proper operation of an RF cavity. The SNS facility now uses three generations of LLRF control hardware. This package is intended to be used in all of them, but is so far only tested on the second ("Interim") generation hardware. It may also be adaptable to future LLRF projects at LBNL, other National Labs, and worldwide.},
doi = {},
url = {https://www.osti.gov/biblio/1245751},
year = {Fri Mar 18 00:00:00 EST 2005},
month = {Fri Mar 18 00:00:00 EST 2005},
note =
}
