Self-stressing test structures used for high-frequency electromigration
Conference
·
OSTI ID:10121208
We demonstrate for the first time high frequency (500 mhz) electromigration at the wafer-level using on-chip, self-stressing test structures. Since the stress temperature, frequency, duty cycle and current are controlled by DC signals in these structures, we used conventional DC test equipment without any special modifications (such as high frequency cabling, high temperature probe cards, etc.). This structure significantly reduces the cost of performing realistic high frequency electromigration experiments.
- Research Organization:
- Sandia National Labs., Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 10121208
- Report Number(s):
- SAND-94-0248C; CONF-940369-1; ON: DE94006142; BR: GB0103012
- Resource Relation:
- Conference: Institute of Electrical and Electronics Engineers (IEEE) international conference on microelectronic test structures,San Diego, CA (United States),22-24 Mar 1994; Other Information: PBD: [1994]
- Country of Publication:
- United States
- Language:
- English
Similar Records
Self-stressing structures for wafer-level oxide breakdown to 200 MHz
Wafer-level pulsed-DC electromigration response at very high frequencies
On-clip high frequency reliability and failure test structures
Conference
·
Wed Feb 01 00:00:00 EST 1995
·
OSTI ID:10121208
+3 more
Wafer-level pulsed-DC electromigration response at very high frequencies
Conference
·
Tue Mar 01 00:00:00 EST 1994
·
OSTI ID:10121208
+1 more
On-clip high frequency reliability and failure test structures
Patent
·
Tue Apr 29 00:00:00 EDT 1997
·
OSTI ID:10121208