CCD operation using the High Speed Imager Test Station
Conference
·
OSTI ID:10109974
- Los Alamos National Lab., NM (United States)
- Lawrence Berkeley Lab., CA (United States)
The use of a high-speed (up to 100 MHz.) programmable pattern generator and special clock driver/translator circuits for clocking solid-state multiple output imagers is discussed. A specific example of clocking a developmental 256 x 512 two-port CCD is illustrated. Reference to a prior report of clocking an eight-port CCD is included. Future use in clocking a CID imager is discussed.
- Research Organization:
- Los Alamos National Lab., NM (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States); Department of Defense, Washington, DC (United States)
- DOE Contract Number:
- W-7405-ENG-36
- OSTI ID:
- 10109974
- Report Number(s):
- LA-UR-92-3487; CONF-9209277-1; ON: DE93003753
- Resource Relation:
- Conference: SPIE: International Society for Optical Engineering meeting,Bellingham, WA (United States),21-25 Sep 1992; Other Information: PBD: [1992]
- Country of Publication:
- United States
- Language:
- English
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